Last update:
Apr 1, 2000
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Integrating High Performance VME, PCI and CPCI processors
into CPU clusters for Data Acquisition and Control Systems
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Luisa Vivolo,
Francois H. Worm,
Martin Weymann
CES - Creative Electronics Systems
Presented by:
Martin Weymann
Data acquisition and control systems using a large number of embedded
VME processors have a long tradition in High Energy Physics. More recently,
CPCI is in some cases considered as an alternative to VME. CES has developed
a processor board architecture optimized for high-throughput deterministic
bus operation, which can used with minimal adaptation on both backplanes.
The RIO3 8064 (VME) and RIOC 4065 (CPCI) are to a large extend software
compatible which helps to develop software solutions almost simultaneously
in both domains. Both boards couple the CPU bus directly to the backplane bus
(VME or CPCI) and to two independent PCI busses. This twin-bus architecture
allows to separate data flows in a similar way than VME/VSB architectures
did in the past. The MFCC 844x, a PowerPC based PMC module is ideally suited
to handle complex I/O protocols or to build multi-CPU clusters coupled by
the carrier boards local PCI bus rather than the backplane bus. The CES PVIC
allows to interconnect distant PCI segments (e.g a VME based processor
cluster and a desktop workstation) using both memory mapped access and DMA
mechanisms. With its 'backplane driver' CES provides an ideal tool to
integrate CPUs interconnected by PCI,VME,CPCI and PVIC into a homogeneous,
network-oriented environment taking full advantage of the high bandwidth and
low latency features of PCI and bakplane busses.
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